ASE is accelerating its advanced packaging technology to meet the soaring demand for AI chips.
The core of this story is a major bottleneck in the AI chip supply chain. TSMC, the world's leading chipmaker, uses a technology called CoWoS to package high-performance AI chips. However, demand has exploded so intensely that TSMC cannot keep up, creating a supply shortage expected to last through 2026. This situation creates a significant "spillover" opportunity for other specialized companies known as OSATs, with analysts estimating this secondary market could be worth about 10% of the total advanced packaging volume.
Furthermore, competitive pressure is mounting. ASE's main rival, Powertech (PTI), has been moving aggressively, announcing its own advanced packaging capacity using a technology called FOPLP. PTI has already secured major customers like AMD and Broadcom, putting immense pressure on ASE to announce a clear, concrete plan to avoid losing ground in this critical new market.
In response, ASE's decision to fast-track its own FOPLP line is highly strategic. The company specifically chose a 310x310mm panel size, which cleverly aligns with TSMC's own next-generation packaging roadmap. TSMC is also starting with a smaller panel to ensure quality and high production yields. By mirroring TSMC's direction, ASE makes its services an easier, more compatible choice for AI chip designers. It's a calculated move to become a seamless part of the broader ecosystem rather than creating a separate standard.
In short, ASE's accelerated plan is a well-timed reaction to three key forces: a clear supply gap in the market, direct pressure from a competitor, and a strategic opportunity to align with the industry leader. This positions the company to capture a vital piece of the booming AI chip market.
- Glossary
- OSAT (Outsourced Semiconductor Assembly and Test): A company that provides third-party semiconductor assembly and testing services.
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC's high-performance packaging technology that stacks chips together to improve speed and efficiency, crucial for AI accelerators.
- FOPLP (Fan-Out Panel-Level Packaging): An advanced packaging method that uses a large, rectangular panel instead of a round wafer, allowing more chips to be processed at once, potentially lowering costs.