Google's Next-Gen TPU Orders Hinge on Packaging Yield; Intel's 90% Rate Pits It Against TSMC's Tight Capacity

Google's decision for its next-generation AI chip packaging is centered on manufacturing yield and cost, creating a competition between TSMC's stable but limited capacity and Intel's emerging alternative.

Analyst Ming-Chi Kuo highlights that Intel's current packaging yield of around 90% is below the 98% mass production standard, resulting in a potential 8-9% cost increase for Google.

This dynamic illustrates the broader industry trends of 'hyperscaler verticalization'—where tech giants design their own chips—and the strategic need to diversify supply chains to mitigate risks and control escalating AI infrastructure costs.

The battle for who will manufacture Google's next-generation AI chips has shifted to a new, critical front: advanced packaging. This isn't just about making the chip anymore; it's about how you assemble it, and the economics of that process are now paramount.

At the heart of this story is a classic supply-and-demand problem. The AI boom has created immense demand for powerful chips. To control costs and performance, Google designs its own, called TPUs (Tensor Processing Units). But making them requires a highly specialized assembly process known as advanced packaging. For years, the undisputed leader in this field has been Taiwan's TSMC. However, with clients like Nvidia taking up most of its capacity, TSMC's production lines are fully booked. This has pushed Google to look for alternatives.

Enter Intel. The American chip giant is making a major push with its own advanced packaging technology, EMIB-T, and is actively courting Google's business. This creates a fascinating contest. On one side, you have TSMC, the proven champion with high stability and manufacturing yield (the percentage of good chips) of around 98%. On the other, you have Intel, the challenger, offering available capacity but with a current yield of about 90%.

That 8% difference in yield might seem small, but it's a massive deal. First, a lower yield directly translates to higher costs. If your yield is 90%, it means 1 in 10 packaged chips is defective. To get 100 good chips, you have to start with about 111, effectively raising your cost per usable chip by nearly 9%. For a company operating at Google's scale, this difference can mean hundreds of millions of dollars. Second, it's why analyst Ming-Chi Kuo states that reaching a ~98% yield is the true bar for mass production; it's the point where costs become predictable and competitive.

Therefore, Google's decision is a strategic one. Does it stick with the reliable but constrained TSMC, or does it bet on Intel's ability to quickly improve its yield? By engaging with Intel, Google not only secures a potential second source but also gains negotiating leverage over TSMC. This move is a textbook example of supply chain diversification, a crucial strategy in today's volatile tech landscape. The spotlight has moved from the chip designer's desk to the factory floor, where the complex art of packaging will determine the future of AI hardware.

Glossary -
TPU (Tensor Processing Unit): A custom-designed chip by Google, optimized for artificial intelligence and machine learning workloads.
Advanced Packaging: A method of integrating multiple semiconductor chips into a single device, essential for creating powerful, efficient AI processors. CoWoS (TSMC) and EMIB-T (Intel) are examples.
Yield: In manufacturing, this refers to the percentage of non-defective items produced in a process. A higher yield means lower costs and greater efficiency.

Google's Next-Gen TPU Orders Hinge on Packaging Yield; Intel's 90% Rate Pits It Against TSMC's Tight Capacity

Analyst Ming-Chi Kuo highlights that Intel's current packaging yield of around 90% is below the 98% mass production standard, resulting in a potential 8-9% cost increase for Google.

Glossary -
TPU (Tensor Processing Unit): A custom-designed chip by Google, optimized for artificial intelligence and machine learning workloads.
Advanced Packaging: A method of integrating multiple semiconductor chips into a single device, essential for creating powerful, efficient AI processors. CoWoS (TSMC) and EMIB-T (Intel) are examples.
Yield: In manufacturing, this refers to the percentage of non-defective items produced in a process. A higher yield means lower costs and greater efficiency.