Hanwha Semitek has announced the development of its first wafer-to-wafer hybrid bonder, the 'SWB1', a strategic move to capitalize on major shifts in the semiconductor industry.
This decision is perfectly timed, driven by two powerful and interconnected trends. First is the surging demand for High-Bandwidth Memory (HBM), essential for AI accelerators. Companies like Micron have already sold out their 2026 supply of HBM4, signaling an urgent need for advanced packaging technologies like hybrid bonding to stack memory chips more efficiently. Samsung is also building a dedicated hybrid bonding line for HBM4, creating a clear domestic market for a Korean equipment supplier like Hanwha.
Second, and perhaps more importantly for the long term, is the advent of Backside Power Delivery Networks (BSPDN). Industry leaders TSMC and Intel are introducing this architecture in their next-generation chips (TSMC's A16 and Intel's 18A). BSPDN separates power and data signals onto opposite sides of the wafer, which requires bonding two wafers together. This transforms wafer-to-wafer bonding from a niche packaging technique into a core manufacturing step for the world's most advanced logic chips.
Hanwha's SWB1 is cleverly positioned to serve both of these markets. While competitors focus heavily on HBM, Hanwha's focus on a logic-oriented wafer-to-wafer bonder provides a crucial hedge. If HBM makers are slow to adopt hybrid bonding, the inevitable shift to BSPDN in logic provides a separate, massive growth driver. This dual-track strategy allows Hanwha to tap into the immediate HBM boom while securing a foundational role in the future of computing hardware.
Ultimately, Hanwha's entry into the hybrid bonder space is backed by its proven experience with other bonding tools and the strong tailwinds from the AI revolution. The company is aiming to capture a piece of a market projected to be worth nearly $2 billion by 2028, establishing itself as a key player in the next generation of semiconductor manufacturing.
- Hybrid Bonding: An advanced semiconductor packaging technique that directly connects chips or wafers using copper-to-copper bonds without solder bumps. This allows for much denser, faster, and more power-efficient connections, crucial for stacking chips in 3D packages like HBM.
- BSPDN (Backside Power Delivery Network): A new chip design architecture where the power delivery network is moved to the backside of the silicon wafer. This separates the power wiring from the signal wiring on the front side, reducing interference and improving performance and power efficiency.