The semiconductor industry is currently discussing a significant change to the HBM4 memory standard, which could reshape the timeline for next-generation AI chips.
At the heart of this conversation is a proposal within JEDEC, the industry's standard-setting body, to increase the maximum stack height for HBM4 memory. Specifically for the upcoming 20-layer (20-Hi) stacks, the plan is to raise the height from the current 775µm to somewhere between 825µm and 900µm. This might sound like a minor technical adjustment, but it signals a major strategic shift in the industry: prioritizing manufacturing stability and yield over the immediate pursuit of maximum performance.
So, why is this happening now? The reason can be traced through a clear causal chain. First, stacking 20 ultra-thin memory chips poses immense physical challenges, increasing the risk of warping, heat issues, and production defects. Instead of forcing an expensive and difficult transition to a new technology called hybrid bonding, relaxing the height standard gives manufacturers more physical breathing room. This allows them to continue using the more mature and reliable MR-MUF packaging process, which is crucial for achieving high yields.
Second, this pragmatic approach aligns perfectly with the needs of major customers. NVIDIA, for its next-generation 'Vera Rubin' platform, has reportedly signaled a preference for supply stability, even suggesting a dual-binning strategy for HBM4 speeds. This means they would accept chips with slightly different performance levels to ensure a steady, high-volume supply. This customer demand for reliability over bleeding-edge specs gives memory makers a strong incentive to favor more manufacturable standards.
Finally, the timing is critical. Both Samsung and SK hynix have recently announced the start of HBM4 shipments. With mass production underway, having a commercially viable and stable standard is more important than ever. The market's reaction confirmed this logic; when news of the potential standard change broke, the stock price of BESI, a leading hybrid bonding equipment maker, fell sharply by 13%. This shows that investors understand that a delay in the transition to next-gen packaging is now a real possibility. This move is a clear choice to balance innovation with the practical realities of mass production, ensuring the AI revolution has a stable foundation to build upon.
- Glossary
- HBM (High Bandwidth Memory): A type of high-performance memory used in GPUs for AI and high-performance computing, made by vertically stacking memory chips.
- JEDEC: The global organization that creates and publishes standards for the microelectronics industry.
- MR-MUF (Mass Reflow Molded Underfill): A packaging technology used in HBM manufacturing to protect the chips and connections. It is the current mainstream technology that hybrid bonding is expected to eventually replace.