A single, highly complex testing process is currently acting as a major bottleneck for the next generation of AI chips.
The demand for more powerful AI is pushing chipmakers to integrate optics directly into chip packages, a technology known as Co-Packaged Optics (CPO) using Silicon Photonics (SiPh). This method replaces traditional copper wires with light to transmit data faster and more efficiently. Major players like Nvidia are targeting 2026 for this transition. However, a significant hurdle has emerged in the manufacturing process, threatening this timeline.
The core of the problem lies in a specific wafer-level test, dubbed 'Insertion 2'. This isn't just any test; it’s a highly complex, double-sided procedure. First, this is necessary because of advanced packaging like TSMC's COUPE technology, which stacks an electronic chip on top of a photonic (optical) chip. To verify the chip works before the expensive final packaging, testers must probe the electrical connections from the top while simultaneously coupling laser light into the optical ports on the bottom. Current testing equipment is struggling to perform this delicate, sub-micron precision task at the speed required for mass production.
This has created what some in the industry are calling a production 'black hole'. The causal chain is clear. First, the demand from AI applications set an aggressive 2026 timeline. Second, TSMC's innovative chip design made this difficult dual-sided test a mandatory step, not an optional one. Third, as test equipment companies like Teradyne and FormFactor release solutions for other parts of the process, this specific 'Insertion 2' step has become the final, unsolved chokepoint.
To skip this test would be a huge gamble. The principle of 'shift-left testing' dictates that finding defects earlier is exponentially cheaper. Scrapping a fully packaged CPO chip, which can cost hundreds or even thousands of dollars, is far more expensive than identifying a faulty component at the wafer stage. Therefore, the race is on for test equipment giants to deliver a reliable, automated solution. The outcome of this race will likely determine whether CPO technology meets its ambitious 2026-2027 rollout schedule.
- Co-Packaged Optics (CPO): A technology that places optical components for data transmission very close to or in the same package as the main processor (like a GPU), enabling faster and more energy-efficient communication.
- Silicon Photonics (SiPh): A technology that uses silicon as an optical medium to create photonic components, allowing data to be transferred by light instead of electricity.
- Wafer-level test: An inspection step performed on the entire silicon wafer before it is cut into individual chips (dies). It helps identify defective chips early in the manufacturing process.