The race to build the most powerful AI chips has entered a critical new phase, and it's all about packaging.
For years, the industry relied heavily on one company, TSMC, and its cutting-edge CoWoS technology to package high-performance AI chips. Think of packaging as creating a mini-circuit board that connects different specialized chiplets (like processors and memory) into one powerful super-chip. The problem is, everyone wants CoWoS, creating a massive supply bottleneck. At the same time, next-generation AI accelerators, like Google's new TPU, are becoming so large that they are physically pushing the size limits of what CoWoS can handle.
This created a pressing need for a viable alternative. Enter Intel and its EMIB technology. For a while, EMIB was seen as a backup plan, but that perception has changed. First, major memory supplier SK Hynix began testing EMIB, lending it credibility. Second, the development of open standards like UCIe has made it easier for companies to mix and match components from different manufacturers, reducing the risk of switching from CoWoS.
This brings us to the main event: chip design giant MediaTek, reportedly at the urging of Google, has decided to use both TSMC's CoWoS and Intel's EMIB. This strategy, known as dual-sourcing, is a game-changer. It's no longer just about securing a Plan B; it's about building a resilient and flexible supply chain from the start. For hyperscalers like Google, this move is crucial. It ensures they can get the massive number of chips they need without being dependent on a single supplier's schedule.
The implications are significant. The ability to guarantee production capacity has suddenly become as important as the performance of the chip itself. This shift elevates Intel Foundry from a challenger to a co-equal player in the high-end packaging arena, fundamentally altering the competitive landscape and giving chip designers more bargaining power than ever before.
- Advanced Packaging: A method of assembling multiple electronic components and semiconductor chips (chiplets) into a single, compact, and high-performance electronic device. It's more complex than traditional packaging and is essential for modern AI chips.
- CoWoS (Chip on Wafer on Substrate): TSMC's industry-leading advanced packaging technology. It stacks chiplets side-by-side on a silicon interposer, enabling high-speed communication between them.
- EMIB (Embedded Multi-die Interconnect Bridge): Intel's advanced packaging technology. It uses small silicon bridges embedded in the package substrate to connect chiplets, offering a flexible and scalable alternative to CoWoS.