NVIDIA CEO Jensen Huang's recent statement about widespread shortages is a clear signal of an AI infrastructure super-boom heading into 2026, one defined by critical supply constraints.
The primary driver behind this is the immense demand generated by NVIDIA's next-generation Rubin platform. Set for mass production in late 2026, the Rubin architecture and its associated NVL72 rack-scale systems are designed to consume exponentially more high-performance components than their predecessors. This isn't a gradual increase; it's a step-function change in the industry's appetite for memory, packaging, and networking hardware.
This has created a multi-front bottleneck, which Huang detailed precisely. First, there's memory. The demand for HBM (High Bandwidth Memory) is so intense that Huang publicly wrote "Make more" on an SK hynix wafer. The expansion into AI PCs with RTX Spark is also creating new demand for LPDDR memory. Second is advanced packaging. TSMC, the sole provider of the essential CoWoS packaging, is expanding capacity but has admitted it will "take a long time" to meet customer demand. Even with a projected 64% capacity increase by the end of 2026, it may not be enough for the Rubin ramp-up.
Finally, there are the interconnects that tie everything together. The industry's shift from 800G to 1.6T optical transceivers is causing a surge in demand for sophisticated components like lasers and silicon photonics, creating a ripple effect that tightens the supply of even basic parts like cables and connectors.
Compounding these issues are geopolitical factors. The U.S. government's move to close loopholes on AI chip exports to Chinese-affiliated companies funnels global demand into a smaller pool of non-Chinese supply chains. This policy-driven concentration of demand makes every existing bottleneck more severe. In essence, the entire AI ecosystem is trying to push through the same few narrow gates simultaneously. Huang's message was not just an observation; it was a call to action for key partners, particularly in Korea's memory and packaging ecosystem, to accelerate their investments for the growth wave of 2026 and beyond.
- HBM (High Bandwidth Memory): A type of high-performance memory stacked vertically, used alongside GPUs to process large AI models quickly.
- CoWoS (Chip-on-Wafer-on-Substrate): An advanced packaging technology from TSMC that places multiple chips on a single interposer, crucial for building powerful AI accelerators.
- Silicon Photonics (SiPh): A technology that uses silicon to create optical devices, enabling faster and more efficient data transfer over light compared to traditional copper wires.