A recent media report suggests that Nvidia's next-generation AI chip, 'Rubin', could see its shipments delayed by one quarter.
The primary reason cited for this potential delay is the significant technical challenge involved in the new HBM4 memory. Unlike its predecessors, HBM4 is moving to a more complex architecture that uses a logic-based 'base die'. This redesign, while promising higher performance, increases manufacturing complexity and integration risks. Industry analysts at TrendForce have consistently highlighted these challenges, making the redesign a plausible root cause for a schedule slip. The entire AI industry is watching closely, as HBM performance is a critical factor in AI model training and inference.
Consequently, this delay has several immediate implications. First, Nvidia is expected to extend the production run of its current flagship, the Blackwell GPU, to fill the supply gap. This would stretch the Blackwell product cycle into late 2026. Second, it creates a valuable window of opportunity for Nvidia's biggest customers—the hyperscalers—who are increasingly developing their own custom AI chips, or ASICs. Google has reportedly already begun increasing its wafer orders for its Tensor Processing Units (TPUs), which are manufactured by TSMC.
This event fits perfectly into the broader narrative of hyperscalers diversifying their compute infrastructure. For years, companies like Google, Meta, Microsoft, and Amazon have been investing heavily in their own silicon to reduce their reliance on Nvidia and to create hardware optimized for their specific workloads. For example, Meta recently unveiled a multi-generation roadmap for its MTIA inference chip, and Microsoft is deploying its Maia series. A delay in Nvidia's latest and greatest offering only strengthens their resolve to pursue this strategy.
From a supply chain perspective, the situation is nuanced. The production of high-end AI chips is severely constrained by advanced packaging capacity, specifically TSMC's CoWoS technology. A temporary pause in Rubin production could free up some of this coveted capacity. This slack would likely be absorbed immediately by increased orders for Google's TPUs and other custom chips. While TSMC is aggressively expanding its CoWoS capacity, demand continues to outstrip supply, making every production slot precious.
In essence, this rumored delay should be viewed as a timing shift rather than a long-term disruption to Nvidia's trajectory. The core issue is the technical hurdle of mass-producing HBM4 memory. If memory suppliers like SK hynix and Samsung can quickly improve their manufacturing yields, the delay could be shorter than expected. If not, hyperscaler ASICs will have a longer period to solidify their position in the market.
- HBM4: High Bandwidth Memory 4, the next generation of stacked DRAM memory crucial for high-performance computing and AI accelerators. Its new architecture adds complexity.
- CoWoS: Chip-on-Wafer-on-Substrate, an advanced 2.5D packaging technology from TSMC used to integrate processors and HBM into a single package.
- Hyperscaler ASIC: Application-Specific Integrated Circuit. Custom-designed chips made by large cloud providers (hyperscalers) like Google (TPU), Amazon (Trainium), and Meta (MTIA) for their specific AI workloads.