Samsung Electronics has officially set its sights on the next frontier of semiconductor technology, announcing a goal to complete R&D for its 1-nanometer (nm) class process by 2030.
This ambitious plan is built on a foundation of recent, tangible success. The most significant factor is the improving yield of its 2nm process (SF2), which has reportedly reached around 60%. This isn't just an internal metric; it's a critical signal to the market that Samsung's transition to the new GAA (Gate-All-Around) transistor architecture is stabilizing. The launch of the Galaxy S26 with a 2nm Exynos chip serves as a public demonstration of this manufacturing capability, building essential customer trust for future technologies.
Of course, this move doesn't exist in a vacuum. It's a strategic response to the relentless pace set by its primary competitor, TSMC. With TSMC already ramping up its 2nm production and having laid out a clear roadmap for 1.6nm and 1.4nm nodes, Samsung needed to present its own long-term vision. The 2030 target for 1nm helps to narrow the 'narrative gap' and assures clients that Samsung is committed to staying at the leading edge.
Fueling this technological arms race are powerful market and policy tailwinds. First, the explosive growth in AI, exemplified by demand for systems like Nvidia's upcoming Rubin platform, requires ever more powerful chips and high-performance memory like HBM4. Samsung's leadership in memory and its foundry business are deeply intertwined here, creating a strong incentive to invest in next-generation nodes. Second, this massive investment is made more viable by government support. Both South Korea's 'K-Chips Act' and the U.S. 'CHIPS Act' provide substantial tax credits and funding, lowering the financial risk of pioneering such costly technology.
The technological path itself is also a logical evolution. The plan is to introduce forksheet transistors, which are seen by industry researchers like imec as the natural successor to the current GAA nanosheet structure. This technology allows for further shrinking of the chip's internal wiring before the industry moves to even more complex designs like CFETs in the 2030s. By aligning with this research consensus, Samsung is making a calculated, not a speculative, bet on the future.
- Yield: The percentage of functional, non-defective chips produced from a single silicon wafer. Higher yield means more efficient and cost-effective production.
- GAA (Gate-All-Around): An advanced transistor structure where the gate material surrounds the channel on all four sides. This provides better electrical control and allows for continued performance scaling compared to older FinFET designs.
- Forksheet Transistor: A next-generation transistor architecture that evolves from GAA. It uses a dielectric wall to separate different types of transistors, allowing them to be placed closer together, which enhances chip density and performance.