SK hynix is making a bold strategic play to reclaim its performance crown in the high-stakes AI memory market by considering TSMC's 3nm process for its next-generation HBM4E.
This decision appears to be a direct response to recent moves by its chief rival. Samsung Electronics recently set a new benchmark by shipping the industry's first HBM4, which utilizes a 4nm process for its base die. By doing so, Samsung not only claimed significant gains in power efficiency but also signaled its capability to reach speeds exceeding 11 Gb/s per pin. This effectively threw down the gauntlet, creating immediate pressure on SK hynix to deliver a solution that could match or, ideally, surpass this new performance standard for its upcoming HBM4E products.
Adding to this competitive pressure is the immense demand from the industry's most important customer: NVIDIA. At its recent GTC 2026 conference, NVIDIA showcased its future 'Rubin Ultra' AI accelerator, which will feature a massive 1 terabyte of HBM4E memory. This sent a clear message that memory bandwidth, capacity, and thermal efficiency remain the most critical bottlenecks in AI systems. SK hynix's plan to use a more advanced 3nm logic die is a direct answer to this challenge, aiming to provide the performance uplift NVIDIA requires.
The timing for such a move is also supported by manufacturing feasibility. TSMC's 3nm node, specifically N3P, is now in high-volume production and offers substantial performance and power improvements over the older 5nm or 4nm technologies. This maturity makes it a viable choice for a complex component like an HBM base die, which must manage over 2,000 high-speed data pathways. The technological foundation is now in place to make this ambitious leap.
Beyond just raw speed, this strategy positions SK hynix for the next major evolution in memory: 'custom HBM'. As major tech companies design their own AI chips (ASICs), they want memory that is more integrated with their unique designs. A cutting-edge 3nm base die allows for customer-specific logic and controllers to be built directly into the memory stack. This transforms the base die from a simple controller into a key piece of customizable technology, deepening the partnership between the memory supplier and the chip designer.
In conclusion, SK hynix's potential shift to TSMC's 3nm process is more than a simple technical upgrade; it's an offensive strategy to redefine performance leadership. If the company can successfully manage the complexities of yield and thermal performance, it could secure the most lucrative orders for the 2026-2027 AI hardware cycle and solidify its dominance in the high-margin memory market.
- HBM (High Bandwidth Memory): A type of high-performance memory that stacks multiple memory chips vertically. This structure allows for much wider data pathways, resulting in significantly higher speed and efficiency, which is crucial for AI accelerators and high-end GPUs.
- Base Die / Logic Die: The bottom-most chip in an HBM stack. It functions as the 'brain' of the memory module, controlling the DRAM chips stacked on top of it and managing the high-speed interface to the main processor. Using a more advanced manufacturing process for this die is critical for boosting overall performance.
- Process Node (e.g., 3nm, 4nm): Refers to a specific generation of semiconductor manufacturing technology. A smaller number, like 3nm (nanometer), generally indicates a more advanced process that can produce smaller, faster, and more power-efficient transistors.