A significant rumor is circulating that Chinese foundry SMIC has achieved a major breakthrough with a new mobile chip, the Kirin 9050, potentially powering Huawei's next flagship phone.
This development is rooted in a strategy of 'using packaging to compensate for process node limitations.' Due to ongoing US export controls, Chinese companies have limited access to the most advanced EUV lithography machines needed for cutting-edge chips. In response, they are pursuing an alternative path: using older DUV equipment combined with innovative 3D stacking technology, specifically Hybrid Bonding, to connect different chiplets vertically. This approach aims to boost overall system performance—improving data bandwidth, power efficiency, and latency—to offset the disadvantages of having less dense transistors.
This strategic pivot didn't happen in a vacuum. The causal chain is clear. First, the global semiconductor industry has already validated this approach. Technologies like TSMC's SoIC and AMD's 3D V-Cache have demonstrated that 3D stacking can deliver substantial performance gains. Second, China has been rapidly developing its domestic supply chain for advanced packaging, with local firms beginning to deliver crucial Hybrid Bonding equipment. Third, SMIC has already proven its ability to push DUV technology to its limits, successfully mass-producing 7nm-class chips (N+2 and N+3 processes), which serve as the foundation for this new stacked design.
However, the central claim that this new chip is “comparable to TSMC's 3nm process” is a bold one that requires scrutiny. Analysis of SMIC's most advanced N+3 process shows it is still a 7nm-class technology, lagging behind the transistor density of true 5nm nodes, let alone 3nm. This implies that any performance parity would have to come almost entirely from the architectural and packaging innovations of the 3D stacking, which would be a remarkable engineering feat.
For now, the narrative rests on strong expectations but weak evidence. The truth of these claims will ultimately be revealed by concrete data. We should look to upcoming semiconductor conferences like ECTC and VLSI for technical papers, and most importantly, to the independent benchmarks and real-world performance tests of Huawei's Mate 90 once it is released.
- DUV (Deep Ultraviolet) Lithography: A method for printing circuits on silicon wafers. It is an older generation technology compared to the more advanced EUV (Extreme Ultraviolet) lithography used for the most cutting-edge chips.
- 3D Stacking (Hybrid Bonding): An advanced packaging technique that connects semiconductor dies directly, one on top of another, using copper-to-copper bonds. This allows for much faster and more efficient communication between chip components compared to traditional methods.
- SoC (System-on-a-Chip): An integrated circuit that combines all or most components of a computer or other electronic system into a single chip. Mobile phone processors are a common example.