TSMC Accelerates Panel-Level Packaging, Igniting New AI Chip Competition with Samsung

TSMC is preparing for mass production of Panel-Level Packaging (PLP) to resolve the production bottleneck of its existing wafer-based packaging (CoWoS) amid soaring AI chip demand.

This move signals a shift in competition with Samsung, which has prior experience in PLP, from a 'wafer' to a 'panel' format, potentially creating a dual-power structure in the advanced packaging market.

The key advantage of PLP is its ability to increase production efficiency by using large square panels, which offer about five times more usable area than traditional round wafers.

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TSMC is officially preparing for the mass production of Panel-Level Packaging (PLP), signaling a major shift in the AI semiconductor packaging race.

This move is driven by a critical bottleneck in the supply chain. The demand for powerful AI accelerators, which combine large logic chips with HBM memory, has outstripped the capacity of traditional packaging methods. TSMC's own advanced packaging technology, known as CoWoS, which is done on round silicon wafers, can no longer keep up with the explosive demand.

To solve this, TSMC is turning to PLP. Instead of a 300mm round wafer, PLP uses a large 600x600mm square panel. This simple change in shape dramatically increases the usable surface area by about five times, as less space is wasted at the edges. This means more chips can be packaged at once, significantly boosting production throughput.

This decision didn't happen overnight; it was the result of several converging factors. First, TSMC itself acknowledged that its advanced process capacity was falling short of demand by a factor of three, highlighting the severe supply shortage. Second, the entire industry, including outsourced assembly and test (OSAT) companies like ASE, began investing in PLP and next-generation glass substrates, creating a clear trend toward larger formats. Third, TSMC's main rival, Samsung, has a head start, having acquired PLP technology back in 2019. This competitive pressure likely accelerated TSMC's timeline.

Ultimately, this sets the stage for a new competitive dynamic. While TSMC dominates wafer-based packaging, Samsung and the Korean ecosystem have a strong position in panel-based technologies. The battle for AI packaging leadership is shifting from a 'wafer game' to a 'panel game', creating a potential dual-power structure in the industry.

[Glossary]

CoWoS (Chip-on-Wafer-on-Substrate): TSMC's high-performance packaging technology that stacks chips on a silicon wafer base. It's powerful but faces capacity limits.
PLP (Panel-Level Packaging): A packaging method that processes chips on a large, rectangular panel instead of a round wafer, aiming for higher efficiency and throughput.
OSAT (Outsourced Semiconductor Assembly and Test): Companies that provide third-party chip assembly, packaging, and testing services.