TSMC is accelerating the development of its next-generation panel-level packaging technology, CoPoS, in direct response to intensifying competition from Intel.
The battleground for AI chip supremacy has decisively shifted. For years, the focus was on producing more advanced silicon wafers. Now, the primary bottleneck is advanced packaging—the technology used to integrate multiple chips and high-bandwidth memory (HBM) into a single, powerful processor. TSMC's current leading technology, CoWoS, has faced persistent shortages despite the company doubling its capacity, highlighting an urgent need for a more scalable solution.
Enter Intel with its new challenger: EMIB-T. This technology allows for significantly larger packages, about 78.5% bigger than TSMC's current offerings. This extra space is critical for housing more processing cores and HBM stacks, which next-generation AI accelerators demand. Reports that Intel is already in talks with hyperscalers like Google and Amazon to use EMIB-T have sent a clear signal that TSMC's market leadership is being challenged.
The causal chain leading to TSMC's strategic shift is clear. First, the existing CoWoS capacity crunch created a market opening for competitors. Second, the technology roadmaps of key customers, particularly NVIDIA's 2028 'Feynman' GPU which features stacked dies, confirmed that future products require precisely the kind of ultra-large packages that EMIB-T offers. Finally, Intel's move to bring EMIB-T into production this year with potential major customers was the catalyst that turned TSMC's long-term plan for panel-level packaging into an urgent priority.
Ultimately, this acceleration is a defensive maneuver to protect TSMC's dominance in the high-end AI sector. The race is no longer just about the smallest transistors but about who can build the biggest, most complex, and most powerful integrated chip packages. TSMC is now in a race against time to get CoPoS ready by 2028, ensuring it can meet the demands of the next wave of AI hardware.
- Advanced Packaging: A method of integrating multiple semiconductor chips, including processors and memory, into a single electronic package. It is crucial for improving performance and power efficiency in high-end devices like AI accelerators.
- CoWoS (Chip on Wafer on Substrate): TSMC's high-performance packaging technology, which has been the industry standard for AI chips but is facing capacity limits.
- EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias): Intel's next-generation packaging technology that enables larger package sizes and improved power delivery, directly competing with TSMC's solutions.