A recent JP Morgan report indicates TSMC is rapidly scaling up its advanced 3D packaging capacity, a critical move to keep pace with the AI revolution.
The core of this story is the transition from current 2.5D packaging, known as CoWoS, to true 3D stacking, called SoIC (System on Integrated Chips). While CoWoS has been the workhorse for today's AI GPUs, next-generation 2-nanometer (2nm) chips demand much more power and data bandwidth than it can efficiently provide. This performance wall is forcing a shift to 3D designs.
So, what's the plan? TSMC is reportedly aiming to boost its SoIC production capacity from an estimated 13,000 wafers per month at the end of 2025 to 40,000 by the end of 2027. This isn't just a minor upgrade; it's a nearly threefold increase in just two years. This aggressive timeline is supported by news of TSMC fast-tracking the equipment installation at its new advanced packaging plants, AP7 and AP8, in Taiwan.
This rapid expansion creates a ripple effect throughout the supply chain. First, it requires immense capital. TSMC's board has already approved a massive $45 billion spending package for new facilities and upgrades, signaling their commitment. Second, it hinges on specialized equipment. The key technology here is hybrid bonding, a process that directly fuses chips together without traditional solder bumps, enabling faster and more efficient connections.
The main bottleneck, and therefore the biggest opportunity, lies with the machines that perform this delicate task: hybrid bonders. Based on current installation figures from the equipment maker Besi, reaching the 40,000 wafer target would require roughly 62 additional bonders. This places Besi, which has a strong partnership with Applied Materials to deliver integrated bonding solutions, in a prime position to capture this surge in demand. This entire narrative is underpinned by strong, sustained AI demand, as reflected in TSMC's recent blockbuster earnings and reports of its capacity being sold out for years to come.
- CoWoS (Chip on Wafer on Substrate): A 2.5D packaging technology where chips are placed side-by-side on an interposer, rather than stacked vertically.
- SoIC (System on Integrated Chips): TSMC's 3D packaging technology that vertically stacks chips using hybrid bonding for higher performance and density.
- Hybrid Bonding: An advanced connection method that directly bonds copper pads on different chips, allowing for much denser and more efficient interconnects than traditional methods.