TSMC has received final approval to equip its second Kumamoto, Japan, factory with advanced 3-nanometer technology, a major step in diversifying the global semiconductor supply chain.
This decision marks a significant upgrade from the original plan, which focused on more mature 6 to 12nm nodes. The pivot to the cutting-edge 3nm process is a direct response to the explosive demand for high-performance chips that power artificial intelligence (AI) and high-performance computing (HPC) applications. Japan is now set to host its first 3nm production base by 2028, a landmark development for the country's tech industry.
The approval is driven by a powerful confluence of factors. First is the overwhelming demand. The world's leading tech companies, from NVIDIA to major cloud providers, are consuming advanced chips faster than they can be made. This has created a severe bottleneck in 3nm manufacturing capacity and advanced packaging, with reports suggesting TSMC's leading-edge capacity is essentially 'sold out' through 2028.
Second, there's a strong geopolitical and policy push. Japan has committed substantial subsidies, up to ¥732 billion, to secure this investment and bolster its domestic semiconductor industry. Simultaneously, the United States is tightening export controls on AI chips to China, which increases the strategic importance of having secure, advanced manufacturing facilities located within allied nations. This move firmly positions Japan as a key hub in the 'friend-shoring' strategy.
Third, TSMC has the financial and operational capacity to execute this ambitious plan. The company's board recently approved a massive capital expenditure (CapEx) budget, earmarking funds for new fabs and expansions. This ensures that the Kumamoto upgrade can proceed alongside other major projects in Arizona, USA, and Germany.
Finally, the project benefits from a crucial learning effect. TSMC's first Kumamoto factory, which began mass production of mature-node chips in late 2025, has already established a local workforce, supply chain, and operational know-how. This experience significantly de-risks the much more complex task of installing and ramping up a 3nm production line.
- 3nm (nanometer): Refers to a generation of semiconductor manufacturing technology. A smaller number generally indicates a more advanced, powerful, and efficient chip.
- Wafer: A thin slice of semiconductor material, such as silicon, upon which microcircuits are etched. A single wafer can contain hundreds or thousands of individual chips.
- CapEx (Capital Expenditure): Funds used by a company to acquire, upgrade, and maintain physical assets such as property, plants, buildings, technology, or equipment.