A recent report from DigiTimes suggests a significant shift in TSMC's strategy for advanced AI chip packaging is underway.
This potential pivot involves three key developments. First, a major expansion of its SoIC technology, a method of stacking chips vertically, is planned for 2027, with most of the new capacity reportedly reserved by NVIDIA. Second, the next-generation CoPoS platform, which uses larger, more efficient panel-level packaging, is now expected to be delayed until late 2030. Third, a related initiative called CoWoP might be suspended due to cost and complexity concerns from key partners.
So, what's driving this change? The story begins with overwhelming demand. For years, the production of advanced AI chips has been limited not by the chips themselves, but by the ability to package them. TSMC has repeatedly stated that demand, led by giants like NVIDIA, far outstrips supply. This scarcity is reinforced by another bottleneck: the supply of HBM (High Bandwidth Memory), which is essential for AI accelerators and is also largely sold out.
Faced with this reality, TSMC's path becomes clearer. The company must meet today's insatiable demand while carefully managing the risks of future technologies. Analysts had already been raising red flags about the technical hurdles for panel-level packaging like CoPoS and CoWoP, citing issues like "warpage" (the panel bending during manufacturing). Pushing forward with an unproven, risky technology could jeopardize the entire AI supply chain.
Therefore, TSMC appears to be making a pragmatic choice: focus on what works and what's next in line. It's extending the life of its reliable workhorse, CoWoS, which remains the industry standard. At the same time, it's pouring investment into SoIC, the next logical step in 3D stacking, whose manufacturing process is more mature. This strategy de-risks the medium-term roadmap and ensures a steady supply for its most important customers. The revolutionary shift to panel-level packaging, it seems, will have to wait a little longer.
- Advanced Packaging: The final stage of semiconductor manufacturing, where a chip is encased in a supportive housing. For AI, this involves complex techniques like stacking multiple chips (like processors and memory) together to achieve higher performance.
- CoWoS / SoIC / CoPoS: These are TSMC's names for different advanced packaging technologies. CoWoS is the current mainstream technology. SoIC is a more advanced 3D-stacking method. CoPoS is a next-generation approach using larger, panel-sized materials instead of traditional round wafers.
- HBM (High Bandwidth Memory): A type of high-performance RAM used in high-end GPUs and AI accelerators. It's stacked vertically to provide much faster data transfer speeds than conventional memory, which is crucial for AI workloads.