TSMC recently announced a pivotal strategy shift that will reshape how the world's most advanced AI chips are built for the rest of the decade.
The core challenge for AI hardware is no longer just about shrinking transistors. It's about data. AI models are incredibly data-hungry, and their performance is often limited by how quickly data can move between the processor and the memory. This has made the chip's packaging—how the processor and memory chips are connected—the new critical bottleneck. The more high-bandwidth memory (HBM) you can connect, the better the performance.
In response, TSMC has laid out a clear, two-part strategy. First, for the chip manufacturing itself, they will stick with their proven and more cost-effective Low-NA EUV technology until at least 2029. They believe they can still achieve necessary performance gains through design improvements without immediately jumping to the next, much more expensive generation of High-NA EUV machines.
Second, and more importantly, they are going all-in on advanced packaging to achieve massive system-level scaling. This involves dramatically enlarging their CoWoS packages to accommodate up to 24 HBM stacks. They also unveiled a roadmap for System-on-Wafer (SoW-X), a groundbreaking technology that aims to turn an entire 300mm silicon wafer into a single, massive integrated system. This is like moving from building a single house to constructing an entire city block on one foundation.
This strategic choice marks a fundamental shift in the industry's focus. The primary driver of AI performance scaling is moving from lithography (making things smaller) to packaging and memory integration (making things bigger and more connected). Consequently, investment and value are expected to flow increasingly towards the supply chains for packaging, testing equipment, and especially HBM.
This doesn't mean High-NA EUV is irrelevant. Competitors like Intel are moving forward with High-NA to simplify their manufacturing processes. For ASML, the sole supplier of these machines, it signals a change in its customer mix—stronger demand from Intel and memory makers, while its largest customer, TSMC, waits. The future of AI chips is now on two diverging paths: TSMC's path of massive integration and its rivals' path of next-generation lithography. This competition will define the semiconductor landscape for years to come.
- High-NA EUV: An extremely advanced and expensive lithography technology used to print the smallest features on a chip. 'NA' stands for Numerical Aperture, and a higher NA allows for finer details.
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC's flagship advanced packaging technology that stacks and connects multiple chips, including processors and HBM, on a single base layer, enabling high performance.
- System-on-Wafer (SoW): A radical approach to chip design that integrates all the components of a complete computer system onto a single silicon wafer, eliminating the need for a traditional circuit board.