TSMC is reportedly forming a strategic alliance with key suppliers to develop the next generation of semiconductor packaging technology.
The explosive growth of AI has created a significant bottleneck in the supply chain. The current go-to technology, CoWoS (Chip-on-Wafer-on-Substrate), is struggling to keep up with demand from major tech companies. This is largely due to the limited production capacity of its core component, the ABF organic substrate. As AI chips become larger and more complex, these organic materials are also hitting their physical limits in terms of size and stability.
To break through this barrier, TSMC is turning to a new solution: glass substrates. This move is driven by a clear causal chain. First, glass offers superior physical properties. It is much flatter and less prone to warping than organic materials, which is critical for building the massive, multi-chip packages required for future AI accelerators. Second, combining glass with Panel-Level Packaging (PLP) allows for a huge leap in manufacturing efficiency. Instead of processing on round 300mm wafers, chips can be manufactured on large rectangular panels, similar to display manufacturing. This drastically increases the usable area, potentially boosting throughput by three to six times and lowering costs once the process matures.
This transition isn't something TSMC can do alone, which explains the strategic collaboration. The reported partnership brings together a powerful trio. TSMC provides the overall chip architecture and customer base through its 3DFabric platform. Ibiden, a world-class Japanese supplier, contributes its deep expertise in substrate manufacturing. Innolux, a panel manufacturing giant, brings essential know-how in handling large-scale panels and related processes. Together, they can accelerate the development of this new technology, which TSMC calls CoPoS (Chip-on-Panel-on-Substrate).
Furthermore, the competitive landscape adds a sense of urgency. Rivals like Intel and Samsung are also aggressively investing in glass substrate technology, with Intel aiming to be the first to mass-produce it. By joining forces with Ibiden and Innolux, TSMC is not just solving a technical problem; it's making a strategic move to secure its leadership in the advanced packaging race, which is becoming just as important as the chip manufacturing process itself.
- Glossary
- CoWoS (Chip-on-Wafer-on-Substrate): An advanced packaging method where multiple chips are placed side-by-side on a silicon interposer, which is then mounted on a substrate. It's currently the standard for high-performance AI chips.
- Glass Substrate: A thin sheet of glass used as the base layer for building semiconductor packages. It offers better electrical performance and dimensional stability compared to traditional organic substrates, allowing for larger and more complex chip designs.
- Panel-Level Packaging (PLP): A manufacturing approach that processes chips on large rectangular panels instead of smaller, round silicon wafers. This method increases the number of chips produced in a single run, improving efficiency and potentially reducing costs.