TSMC is developing a next-generation chip packaging technology called CoPoS, targeting mass production in the second half of 2028.
The core motivation behind this shift is simple: economics. Today's most powerful AI chips are built using TSMC's CoWoS technology, which packages multiple chips together on a single round silicon wafer. As AI accelerators become larger and more complex, fitting these massive rectangular packages onto a round wafer becomes incredibly inefficient. Imagine trying to cut large square cookies from a round sheet of dough—you end up with a lot of wasted space at the edges. This inefficiency drives up costs and limits how many chips can be produced.
CoPoS tackles this problem by moving from 300mm round wafers to large, square glass panels. This is a game-changer for throughput. For an ultra-large chip package, a standard wafer might fit only three units. In contrast, a 510x515 mm square panel can fit around 30 units. That's a tenfold increase in efficiency, which directly translates into lower manufacturing costs for these expensive AI chips. This move is a form of Panel-Level Packaging (PLP), a key trend in the industry.
It's also important to understand what CoPoS is—and what it isn't. Despite some confusion, it does not use a 'glass interposer' or replace the essential ABF materials used today. Instead, CoPoS uses a glass-core substrate. Think of it as a sandwich: the glass forms a flat, stable core, and the traditional build-up layers (made of ABF) are applied on top. The chips are then mounted on these layers. This structure leverages the mechanical stability of glass to prevent the large packages from warping, while still using proven materials for the intricate wiring.
So, who needs this? The prime candidate is NVIDIA. Their 2028 'Feynman' platform is expected to feature stacked GPU dies, creating a much thicker, hotter, and more complex module. The stability offered by a glass core and the cost savings from panel-level production make CoPoS a natural fit for such an ambitious design.
In essence, CoPoS is TSMC's strategic answer to the growing pains of the AI era. By transitioning to more efficient square panels and stable glass-core substrates, TSMC is paving the way for the even larger and more powerful AI accelerators of the future.
- CoWoS: Chip-on-Wafer-on-Substrate. A high-performance packaging method where chips are placed on a silicon interposer, which sits on a substrate.
- Panel-Level Packaging (PLP): A packaging method that uses large, rectangular panels instead of round wafers to increase production efficiency and lower costs.
- Substrate: The base layer that provides electrical and mechanical support for the semiconductor chips in a package.