TSMC Unveils A13 and N2U Processes, Extending Low-NA EUV to Counter High-NA Costs and Tool Scarcity

TSMC announced new A13 and N2U chip processes that will continue to use existing Low-NA EUV technology, rather than adopting the newer, more expensive High-NA EUV tools.

This decision is driven by the high cost of High-NA equipment and a shortage of manufacturing tools, allowing TSMC to rapidly expand capacity for AI chips while maintaining cost efficiency.

This strategy contrasts with competitors like Intel who are early adopters of High-NA, positioning TSMC to maximize returns on its established technology while managing supply chain risks.

TSMC has announced its next-generation A13 and N2U processes, strategically choosing to extend its current technology rather than immediately jumping to the next big thing.

The core of this decision is a pragmatic focus on economics and speed. First, there's the significant price difference. High-NA EUV scanners, the next-generation tools, cost around $380-$400 million each, while the current Low-NA EUV scanners are in the $235-$265 million range. By sticking with the proven Low-NA technology, TSMC can avoid billions in capital expenditure that can be better used to build more overall capacity.

Second, the timing couldn't be more critical. The demand for AI chips is surging, but the supply of the necessary manufacturing tools is tight, as shown by SK hynix's recent massive order for Low-NA scanners. By reusing its vast, existing fleet of Low-NA tools, TSMC can add production capacity much faster to meet the immediate, ravenous demand from the AI industry.

This isn't a shot in the dark; it's a proven playbook. TSMC already successfully brought its 2nm (N2) node into volume production using Low-NA technology in late 2025. This success de-risks the plan to push the technology further with techniques like multi-patterning, giving the company confidence that it can deliver performance gains without the brand-new tools.

This move also draws a clear line in the sand against competitors like Intel, which has invested heavily in being the first to adopt High-NA. TSMC is essentially betting that perfecting its current methods to squeeze out more performance is a smarter, more profitable path for the near term than absorbing the cost and teething issues of brand-new technology.

Ultimately, TSMC's strategy is about maximizing the return on its massive investment in Low-NA EUV. It’s a calculated move to navigate a market defined by soaring AI demand and limited tool supply, prioritizing immediate, cost-effective production over a premature leap into the next generation of tools.

EUV (Extreme Ultraviolet) Lithography: A technology using extremely short wavelength light to print complex patterns on silicon wafers, essential for making the most advanced chips.
Low-NA vs. High-NA: 'NA' (Numerical Aperture) refers to a scanner's ability to collect light and resolve fine details. High-NA is the next generation, offering higher precision for future chips but at a much greater cost and complexity. Low-NA is the current, mature technology being used for mass production.
Multi-patterning: A technique used to create finer patterns on a chip than a lithography tool can achieve in a single pass. It involves using multiple exposure and etch steps, which adds complexity but allows chipmakers to extend the life of their existing equipment.

TSMC Unveils A13 and N2U Processes, Extending Low-NA EUV to Counter High-NA Costs and Tool Scarcity

TSMC announced new A13 and N2U chip processes that will continue to use existing Low-NA EUV technology, rather than adopting the newer, more expensive High-NA EUV tools.

This decision is driven by the high cost of High-NA equipment and a shortage of manufacturing tools, allowing TSMC to rapidly expand capacity for AI chips while maintaining cost efficiency.

This strategy contrasts with competitors like Intel who are early adopters of High-NA, positioning TSMC to maximize returns on its established technology while managing supply chain risks.

TSMC has announced its next-generation A13 and N2U processes, strategically choosing to extend its current technology rather than immediately jumping to the next big thing.

EUV (Extreme Ultraviolet) Lithography: A technology using extremely short wavelength light to print complex patterns on silicon wafers, essential for making the most advanced chips.
Low-NA vs. High-NA: 'NA' (Numerical Aperture) refers to a scanner's ability to collect light and resolve fine details. High-NA is the next generation, offering higher precision for future chips but at a much greater cost and complexity. Low-NA is the current, mature technology being used for mass production.
Multi-patterning: A technique used to create finer patterns on a chip than a lithography tool can achieve in a single pass. It involves using multiple exposure and etch steps, which adds complexity but allows chipmakers to extend the life of their existing equipment.